The present invention relates to nonvolatile semiconductor memories with a NAND logic memory cell structure, and more particularly to highly integrated nonvolatile semiconductor memories having a unit memory cell structure suitable for high speed operation and a low power supply voltage.
A nonvolatile semiconductor memory such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) or MROM (Mask Read Only Memory) usually has a NAND logic memory cell structure in order to reduce power consumption and improve integration density. NAND unit memory cells are arranged in memory strings, and there are a plurality of NAND unit memory cells formed in a matrix of rows and columns on a chip. As the integration density of a memory device is increased, the spacing between memory strings necessarily becomes narrower, and requires design-rules that are much more difficult to practically implement. Further, the spacing between bit lines also decreases and the line width of each bit line also narrows. These phenomena may create coupling capacitance between bit lines and increase bit line resistance, thus reducing the efficiency of signal transmission through the bit line. Therefore, it is difficult to fabricate a highly integrated nonvolatile semiconductor memory device having a high operation speed and improved operating characteristics using a low power supply voltage.
FIG. 1 shows memory access transistors of typical unit memory cells having a NAND logic structure. Two memory strings are connected to one bit line BL and each memory string consists of two string select transistors controlled by signals on string select lines SSL1, SSL2 and memory transistors controlled by signals on word lines WL1-WLn. Two string select transistors, enhancement mode transistor 2 and depletion mode transistor 12, are each connected to a bit line contact portion 10 and connected serially to respective memory strings such that string select signals SSL1, SSL2 select one of the memory strings. All memory transistors 6, 16, 8, 18 are enhancement mode transistors. During a data reading operation, if memory transistor 6 of string #1 is selected, a read data signal is applied to the bit line BL. Supply voltage VCC and ground voltage 0 V are respectively applied to first and second string select signals SSL1 and SSL2. The ground voltage 0 V is applied to word line WL1 and the supply voltage VCC is applied to all other word lines WL2, . . . , WLn, thereby reading out the data stored in the memory transistor 6.
If there are 8 memory transistors within one unit string and the semiconductor memory is 16 Mbits (mega=22.sup.20) in size, the architecture of a cell array may have a layout such as 1K.times.16K (K=2.sup.10), 2K.times.8K or 4K.times.4K. If a 2K.times.8K layout is chosen, 1K unit strings are serially connected to one bit line. Loading on each bit line within the chip is greatly increased, resulting in a delay of the signal transmission or in a malfunction at a low power supply voltage. Moreover, capacitances are generated, for example, between the substrate and the metal bit line, between the polysilicon layer forming a word line and the metal line formed on the polysilicon layer, and between metal lines. There are also drain overlap capacitances of the enhancement made memory transistors nearest to the bit line. In order to achieve a more highly integrated nonvolatile semiconductor circuit of 64 Mbits, 256 Mbits or more in which the degree of memory cell integration is increased and the power supply voltage is lowered, these problems must be overcome.
Increased bit line loading also creates junction capacitance at the bit line contact portion 10. FIG. 2 shows a cross sectional view of the bit line contact portion 10 of FIG. 1. Bit line 22 formed of metal is in contact with N.sup.+ active region 24. N.sup.+ active regions 26 are used as a drain and a source of a transistor, and gate electrodes 32A to 32D of transistors which are formed with polysilicon are used as connecting means within the chip. In the construction of FIG. 2, the N.sup.+ active region 24 is formed at the bit line contact portion in addition to the N.sup.+ active regions 26 used as the drain and source regions of a transistor, in order to enhance mobility of a carrier. The junction capacitance of the N.sup.+ active region 24 is based on its impurity concentration. This junction capacitance exists at a large number of bit line contact portions within the chip, resulting in the delay of the signal transmission. If gate electrode 32C is a control terminal of a depletion mode transistor and gate electrode 32D is a control terminal of an enhancement mode transistor, overlap capacitance is generated during a stand-by operation or a data access operation, since a ground voltage is applied as the control voltage of the enhancement mode transistor as indicated by a dashed-line circle 36. Consequently, in a very large scale semiconductor memory of 64 Mbits or more, high speed operation is hindered and malfunctions occur at a low power supply voltage during a reading operation.